This section introduces aspects that may help facilitate a better understanding of the disclosure. Accordingly, these statements are to be read in this light and are not to be understood as admissions about what is or is not prior art.
The growth in data sets and increase in the number of cores place high demands on the memory systems of modern computing platforms. Complementary metal oxide semiconductors (CMOS) memories including static read access memory (SRAM) and embedded dynamic read access memory (DRAM) have been the mainstays of memory design for the past several decades. However, recent technology scaling challenges in CMOS memories, along with an increased demand for memory capacity and performance, have fueled an active interest in alternative memory technologies. One such alternative memory technology is Spintronic memories.
Spintronic memories have emerged as a promising candidate for future memories based on a plurality of advantageous characteristics such as non-volatility, high density, and near-zero leakage. In particular, Spin Transfer Torque Magnetic RAM (STT-MRAM) has garnered significant interest. Regardless of the technology, movement of data from bit cells in the memory to the processor and back (across the bit lines, memory interface, and system interconnect) is a bottleneck to performance and energy efficiency of computing systems. One way of addressing this bottleneck is in-memory computing, whereby a close integration of logic and memory, variedly referred to in the literature as logic in-memory, compute-in-memory, processing-in-memory, etc., occurs. In-memory computing may be classified into three categories—moving logic closer to memory, performing computations within memory structures, and embedding nonvolatile storage elements within logic. The first two approaches address the efficiency of performing active computation, whereas the third addresses the challenge of memory energy during idle periods.
Performing computations within memory structures requires enabling multiple word lines, investigated by others to perform computations within off-chip non-volatile memories (NVM)s. However, process variations, particularly with respect to on-chip memories, and the typical stochastic nature of STT-MRAM make the solutions provided in the art for on-chip in-memory computing inadequate, and particularly for on-chip STT-MRAM.
Therefore, there is an unmet need for a novel architecture and method to utilize in-memory computing with on-chip STT-MRAM memories.